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你想要的过孔和加工出来的过孔有多大差别?
2023-09-19
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有时候一句话就能改善高速信号的通道损耗???
2023-09-18
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加泪滴对DDRX等信号S参数有什么影响
2023-09-18
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参考平面很重要,为啥这里要挖掉?
2023-08-28
![图片1](http://edadoc.com/upload/images/article/20230814/16919933731335824.png)
看似多余实则无用的金手指镀金引线对高速信号有影响吗?
2023-08-14
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DDR5这么快,为啥还能那么稳?
2023-06-28
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DDR跑不到速率后续来了,相邻层串扰深度分析!
2023-06-06
![图片1](http://edadoc.com/upload/images/article/20230602/16856896763197379.png)
DDR跑不到速率,调整下PCB叠层就搞掂了?
2023-06-02
![图片1](http://edadoc.com/upload/images/article/20230516/16842293264461054.png)
解析DDR设计中容性负载补偿的作用
2023-05-16
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线宽变大,损耗变小;线宽无限大,损耗无限小?
2023-05-11
![图片1](http://edadoc.com/upload/images/article/20230417/16817145768573300.png)
年少不知回损好,却把插损当作宝
2023-04-17
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高速数字信号VS射频信号,到底哪个更难设计?
2023-04-12
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芯片那么小,封装基板走线损耗能大到哪去?
2023-04-07
![图片2](http://edadoc.com/upload/images/article/20230321/16793893197237543.jpg)
链路上小段线的阻抗突变到底会不会影响信号质量?
2023-03-21
![图片1](http://edadoc.com/upload/images/article/20221212/16708363485693582.jpg)
性能逆天的这种电容,你见过吗?
2022-12-12
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封装基板出厂100欧姆,测试85欧姆?
2022-12-07
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PCB信号仿真之为什么DDR走线要同组同层?
2022-12-01
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PCB设计仿真之探讨源端串联端接
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